They can check the CUSB2 core during VHDL simulation.
Hardware test
To check if the CUSB2 supports both Full and High-Speed transfer rates, the CUSB2 sample application should be made. After the sample application (for example our CUSB2 demo) is connected to the USB 2.0 host, it will start working at 12Mbps and then it automatically switches to 480Mbps mode (speed negotiation protocol). It can be observed using digital analyzer connected to the CUSB2 UTMI interface. (The UTMI is standard described by Intel).
Note:
The CUSB2 core requires 30MHz or 60MHz clock generator. To support 480Mbps the CUSB2 core uses external USB2.0 transceiver that serializes/deserializes the USB data.
To support high-bandwidth applications (480Mbps=60MB/s) , the CUSB2 uses the SlaveFIFO interface that enables direct access to the endpoint buffers. SlaveFIFO can be controlled by hardware so data can be transferred without processor intervention.
8051 Core 의 compile & debugging 환경
Anyone using the 8051 will need to use software development tools for the program they plan to run. There are many available tools in the market including Keil, Tasking, etc. Anyone of them will work with the 8051 cores.
PCI Core 의 Driver 제공 여부
We do not supply a device driver with the the PCI cores since any customer design requires a new driver. We recommend using Jungo's WinDriver as the simplest solution for device driver development.
WinDriver supports all MS Windows platforms as well as Linux, Solaris and VxWorks.
See the following link for more details: http://www.jungo.com/windriver.html
Download here: http://www.jungo.com/dnload.html
PCI-M32 Core 와 DMA32 core 의 크기
Xilinx implementation numbers:
PCI-M32 = 184 - 284 Slices - exact size depends on the number of BARs
DMA32 = 200 slices (additional area for the built in DMA in the PCI-M32 core)
CAST 에서 제공하는 Evaluation core
Altera OpenCore - with this the user can actually place&route the design, even add their own logic too. Altera has a built-in simulator inside Quartus, so the user can also do some limited simulations. The user is not allowed to program a part.
Compiled ModelSim or Cadence library - For customers not using Altera this is the method for evaluations. We compiled the RTL core into a library and deliver that along with the source code for the testbench and vectors.
In very special cases (usually requires some form of payment) we allow the user to program a FPGA to verify the functionality of the core. We don't really like this method since it can be very support intensive. So it needs to be a large order to be worth.
CAST Core 의 FPGA 또는 FAB 에서의 검증에 관하여
Our cores are written with generic VHDL/Verilog so that they can be targeted in both ASIC and FPGA technologies.
The only functions that are technology dependent are the memories. For FPGAs we try to take advantage of their embedded memory structures.
For ASIC the user has to instantiate the proper memory available for their technology.
About 50% of our customers are ASIC users, so your customers should not be concerned.
As long as they are on maintenance we can help them with their questions.
What we cannot do is help them learn how to use their ASIC tools. That would be the job of the tool vendor.
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